CN102655179A - Method for preparing black silicon - Google Patents

Method for preparing black silicon Download PDF

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Publication number
CN102655179A
CN102655179A CN2011100508871A CN201110050887A CN102655179A CN 102655179 A CN102655179 A CN 102655179A CN 2011100508871 A CN2011100508871 A CN 2011100508871A CN 201110050887 A CN201110050887 A CN 201110050887A CN 102655179 A CN102655179 A CN 102655179A
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silicon
silicon chip
nano
radio
frequency power
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CN2011100508871A
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苏晓东
辛煜
邹帅
陈军
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Suzhou University
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Suzhou University
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

The embodiment of the invention discloses a method for preparing black silicon, comprising the following steps of: cleaning the surface of a silicon wafer; depositing silver nanoparticles on the surface of the silicon wafer to form a silver nanoparticle mask; and carrying out plasma etching on the silicon wafer with the silver nanoparticle mask to form a light trapping nanostructure on the surface of the silicon wafer. The silver nanoparticles can be used for reducing the damage of ion bombardment to the silicon wafer in the plasma etching process and preparing uniformly-distributed textured structural layers and have lower surface reflection rate and longer current carrier service life, therefore, by using the method, the black silicon which is strong in light absorption characteristic and extremely sensitive to light can be formed on the silicon wafer, and meanwhile, the method is lower in cost, simple in process flow, capable of directly preparing large-area black silicon and high in preparation efficiency.

Description

The silicon method is deceived in a kind of preparation
Technical field:
The present invention relates to the semi-conducting material preparing technical field, relate in particular to a kind of method for preparing black silicon.
Background technology:
Black silicon (black silicon) is meant and almost can absorbs extremely low silicon face of all visible lights, reflectivity or silica-base film.Black silicon is the revolutionary novel semiconductor material of a kind of electronic industry; Compare with general silicon material structure; Black silicon has very strong extinction ability; Be applied to optical pickocff or solar cell if will deceive silicon, the light receiving efficiency of optical pickocff can improve hundreds of times so, and the photoelectric conversion efficiency of solar cell also is able to significantly improve.Therefore, black silicon has very important application potentiality in fields such as photovoltaic cell, hypersensors.
At present; A kind of method for preparing black silicon of the prior art is: adopt the femto-second laser preparation; It utilizes femtosecond laser to shine silicon chip being full of under the vacuum environment of halogen gas, produces the peak structure of micron dimension in the silicon face laser irradiation region, forms the spike array of forest shape.This nanometer falls into the optical surface structure and helps reducing the light reflection, strengthens the absorbability of silicon face to light.Yet, adopting the black silicon of femto-second laser preparation, technology is quite complicated, and process control is loaded down with trivial details, and equipment cost is very expensive, safeguards inconvenience, is unfavorable for the large-scale manufacturing.
The method of the black silicon of another kind of preparation of the prior art is: based on the black silicon of no mask deep reaction ion etching preparation, through the technological parameter of the black silicon of control deep reaction ion etching preparation, adopt the mode of etching and passivation alternately silicon chip to be handled.The technological parameter that is adopted comprises: gas flow, the dull and stereotyped power of etching, the dull and stereotyped power of passivation, coil power and etching, the cycle of passivation, temperature.
Though the preparation method based on no mask deep reaction ion etching is higher than the preparation method's efficient that adopts femto-second laser; Cost is lower; But because it needs alternately silicon chip to be carried out etching and Passivation Treatment promptly charges into etching gas successively repeatedly, and regulate corresponding flow, power, time and environmental parameter.Therefore, utilize this method to prepare black silicon, problem such as exist that technology is comparatively complicated, process control is more loaded down with trivial details and efficient is low.
Summary of the invention
For solving the problems of the technologies described above, the object of the present invention is to provide a kind of method for preparing black silicon, with in the black silicon preparation cost of control, simplify technological process, and improve preparation efficiency.
For this reason, the embodiment of the invention provides following technical scheme:
The silicon method is deceived in a kind of preparation, comprising:
Silicon chip surface is carried out clean;
At silicon chip surface depositing nano silver particle, form the nano-Ag particles mask;
The silicon chip that will have the nano-Ag particles mask carries out plasma etching, thereby forms the nanometer light trapping structure at silicon chip surface.
Further, adopt RCA standard cleaning method that silicon chip surface is carried out clean.
Further, adopt magnetron sputtering technique at silicon chip surface depositing nano silver particle.
Further, said magnetron sputtering technique comprises:
Silicon chip is put into magnetron sputtering vacuum chamber, and be evacuated to 1x10 -3Pa;
Flow with 40sccm feeds argon gas to vacuum chamber, regulates gas pressure in vacuum to 0.5Pa;
After treating that gas pressure in vacuum is stable, add radio-frequency power, regulate adaptation to build-up of luminance, sputter 2~20 seconds;
Sputter is closed radio-frequency power supply after accomplishing, and stops air feed, is evacuated to 1x10 -3Pa;
Close extract system, and feeding nitrogen advances, and vacuum chamber is interior to take out silicon chip to 1 atmospheric pressure.
Further, the grain size of the nano-Ag particles in the said nano-Ag particles mask is 20~80nm.
Further, said plasma etching comprises:
Silicon chip is put into plasma etch chamber, and be evacuated to 1x10 -3Pa;
Flow with 40~50sccm feeds SF 6, and feed O with the flow of 2~10sccm 2
Regulating high valve makes the air pressure in the plasma etch chamber remain on 1Pa;
Top electrode adds the radio-frequency power 250W that frequency is 27.12MHz, and bottom electrode adds the radio-frequency power 50W that frequency is 13.56MHz, etching 5~10 minutes;
Close radio-frequency power supply, stop air feed, be evacuated to 5x10 -3Pa;
Close extract system, inflated with nitrogen takes out silicon chip after advancing plasma etch chamber to 1 atmospheric pressure.
Further, said silicon chip is monocrystalline silicon piece or polysilicon chip.
Compared with prior art, technique scheme has the following advantages:
In the technical scheme that the embodiment of the invention provided, prepare the silver-colored particle mask layer of nano-scale, carry out the plasma dry etching through mask layer more afterwards at silicon chip surface; The nanometer-level silver particle can reduce the damage that the bombardment of plasma etch process intermediate ion causes silicon chip; And can make equally distributed textured structure layer, it has lower surface reflectivity and higher carrier lifetime, use this method can on silicon chip, form have very strong extinction characteristic, to its responsive black silicon of auroral poles; This method cost is lower simultaneously; Technological process is simple, and can directly prepare large-area black silicon, has higher preparation efficiency.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Silicon method flow sketch map is deceived in the preparation that Fig. 1 provides for embodiment one;
The silicon chip surface that Fig. 2 provides for embodiment one and the ESEM micro-organization chart of nano-Ag particles;
Silicon chip surface ESEM micro-organization chart after the plasma etching that Fig. 3 provides for embodiment two;
The reflectivity sketch map of the silicon cell that Fig. 4 provides for embodiment two.
Embodiment
For in the black silicon preparation cost of control, to simplify its technological process, and improve black silicon preparation efficiency, the embodiment of the invention provides a kind of preparation to deceive the silicon method, comprising:
Silicon chip surface is carried out clean;
At silicon chip surface depositing nano silver particle, form the nano-Ag particles mask;
The silicon chip that will have the nano-Ag particles mask carries out plasma etching, thereby forms the nanometer light trapping structure at silicon chip surface.
In the technical scheme that the embodiment of the invention provided, prepare the silver-colored particle mask layer of nano-scale, carry out the plasma dry etching through mask layer more afterwards at silicon chip surface; The nanometer-level silver particle can reduce the damage that the bombardment of plasma etch process intermediate ion causes silicon chip; And can make equally distributed textured structure layer, it has lower surface reflectivity and higher carrier lifetime, use this method can on silicon chip, form have very strong extinction characteristic, to its responsive black silicon of auroral poles; This method cost is lower simultaneously; Technological process is simple, and can directly prepare large-area black silicon, has higher preparation efficiency.
It more than is the application's core concept; To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention carried out clear, intactly description, obviously; Described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
A lot of details have been set forth in the following description so that make much of the present invention; But the present invention can also adopt other to be different from alternate manner described here and implement; Those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed specific embodiment.
At first the english abbreviation that possibly use among the embodiment is described:
Sccm: gas flow unit, standard milliliter per minute; Pa: the barometric millimeter of mercury; MHZ: megahertz; SF 6: sulphur hexafluoride; O 2: oxygen; Nm: nanometer.
Embodiment one:
For in the black silicon preparation cost of control, to simplify its technological process, and improve black silicon preparation efficiency, present embodiment provides a kind of preparation to deceive the silicon method, and is as shown in Figure 1, is a kind of schematic flow sheet of this method, and this method may further comprise the steps:
Step S101 carries out clean to silicon chip surface;
Step S102 at silicon chip surface depositing nano silver particle, forms the nano-Ag particles mask;
Step S103, the silicon chip that will have the nano-Ag particles mask carries out plasma etching, thereby forms the nanometer light trapping structure at silicon chip surface.
Concrete, among the step S101, can adopt the RCA cleaning of semiconductor industrywide standard, remove staining of silicon chip surface.The RCA that uses at present cleans and comprised for four steps mostly; Promptly carrying out acidic oxidation with vitriolated acid hydrogen peroxide earlier cleans; Carry out alkaline oxygenated cleaning with the alkalescent hydrogen peroxide that contains amine again, then clean, carry out acidic oxidation with hydrochloric acid hydrogen peroxide at last and clean with rare hydrofluoric acid solution; In the middle of each the cleaning, all to use ultra-pure water (DI water) to carry out rinsing, carry out drying with low boiling point organic solvent more at last.
Among the said step S102, can adopt magnetron sputtering technique at silicon chip surface depositing nano silver particle, to form the nano-Ag particles mask.Through the technological parameter in the control magnetron sputtering process, the grain size of the nano-Ag particles in the control nano-Ag particles mask is 20~80nm.As shown in Figure 2, be the ESEM micro-organization chart of silicon chip surface and nano-Ag particles, (grain size is 20~80nm) to be evenly distributed to nano-Ag particles wherein, has formed the mask in the step S103 ionic medium body etching technics.
Wherein, be example with P type polysilicon chip, the magnetron sputtering technique described in the step S102 specifically can may further comprise the steps:
Step S102a: will pass through the P type polysilicon chip that RCA cleaned and put into magnetron sputtering vacuum chamber, and be evacuated to 1x10 -3Pa;
Step S102b: the flow with 40sccm feeds argon gas to vacuum chamber, regulates gas pressure in vacuum to 0.5Pa;
Step S102c: after treating that gas pressure in vacuum is stable, add radio-frequency power, regulate adaptation to build-up of luminance, sputter 2~20 seconds;
Step S102d: sputter is closed radio-frequency power supply after accomplishing, and stops air feed, is evacuated to 1x10 -3Pa;
Step S102e: close extract system, feed nitrogen then and advance in the vacuum chamber, treat that the vacuum chamber internal gas pressure reaches after 1 atmospheric pressure, opens vacuum chamber, and silicon chip is taken out.
Next, the plasma etching described in the step S103 specifically can may further comprise the steps:
Step S103a puts into plasma etch chamber with silicon chip, and is evacuated to 1x10 -3Pa;
Step S103b is with the flow feeding SF of 40~50sccm 6, and feed O with the flow of 2~10sccm 2
Step S103c regulates high valve and makes the air pressure in the plasma etch chamber remain on 1Pa;
Step S103d, top electrode add the radio-frequency power 250W that frequency is 27.12MHz, and bottom electrode adds the radio-frequency power 50W that frequency is 13.56MHz, etching 5~10 minutes;
Step S103e closes radio-frequency power supply, stops air feed, is evacuated to 5x10 -3Pa;
Step S103f closes extract system, feeds nitrogen then and advances in the vacuum chamber, treats that the vacuum chamber internal gas pressure reaches after 1 atmospheric pressure, opens vacuum chamber, and silicon chip is taken out.
In the plasma etching etching process, nano-Ag particles can reduce the damage that the ion pair silicon chip surface causes, and can make equally distributed suede structure.Referring to shown in Figure 3, be the silicon chip surface ESEM micro-organization chart after the plasma etching, silicon chip surface has formed uniform nanometer light trapping structure.
It is in the technology of the black silicon of feedstock production that the black silicon method of the preparation that this enforcement provides can be used with monocrystalline silicon piece or polysilicon chip; Method through the black silicon of this preparation; Can on silicon chip surface, form be evenly distributed, size is the micro-structural of 150~1000nm controllable size, and its matte reflectivity is lower than 2%.Referring to shown in Figure 4, for using the reflectivity sketch map of the silicon cell that this method finally obtains.
In the black silicon method of the preparation that present embodiment provides, prepare the silver-colored particle mask layer of nano-scale, carry out the plasma dry etching through mask layer more afterwards at silicon chip surface; The nanometer-level silver particle can reduce the damage that the bombardment of plasma etch process intermediate ion causes silicon chip; And can make equally distributed textured structure layer, it has lower surface reflectivity and higher carrier lifetime, use this method can on silicon chip, form have very strong extinction characteristic, to its responsive black silicon of auroral poles; This method cost is lower simultaneously; Technological process is simple, and can directly prepare large-area black silicon, has higher preparation efficiency.
Various piece adopts the mode of going forward one by one to describe in this specification, and what each part stressed all is and the difference of other parts that identical similar part is mutually referring to getting final product between the various piece.To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.

Claims (7)

1. one kind prepares black silicon method, it is characterized in that, comprising:
Silicon chip surface is carried out clean;
At silicon chip surface depositing nano silver particle, form the nano-Ag particles mask;
The silicon chip that will have the nano-Ag particles mask carries out plasma etching, thereby forms the nanometer light trapping structure at silicon chip surface.
2. the silicon method is deceived in preparation according to claim 1, it is characterized in that:
Adopt RCA standard cleaning method that silicon chip surface is carried out clean.
3. the silicon method is deceived in preparation according to claim 1, it is characterized in that:
Adopt magnetron sputtering technique at silicon chip surface depositing nano silver particle.
4. the silicon method is deceived in preparation according to claim 3, it is characterized in that said magnetron sputtering technique comprises:
Silicon chip is put into magnetron sputtering vacuum chamber, and be evacuated to 1x10 -3Pa;
Flow with 40sccm feeds argon gas to vacuum chamber, regulates gas pressure in vacuum to 0.5Pa;
After treating that gas pressure in vacuum is stable, add radio-frequency power, regulate adaptation to build-up of luminance, sputter 2~20 seconds;
Sputter is closed radio-frequency power supply after accomplishing, and stops air feed, is evacuated to 1x10 -3Pa;
Close extract system, and feeding nitrogen advances, and vacuum chamber is interior to take out silicon chip to 1 atmospheric pressure.
5. the silicon method is deceived in preparation according to claim 1, it is characterized in that:
The grain size of the nano-Ag particles in the said nano-Ag particles mask is 20~80nm.
6. the silicon method is deceived in preparation according to claim 1, it is characterized in that said plasma etching comprises:
Silicon chip is put into plasma etch chamber, and be evacuated to 1x10 -3Pa;
Flow with 40~50sccm feeds SF 6, and feed O with the flow of 2~10sccm 2
Regulating high valve makes the air pressure in the plasma etch chamber remain on 1Pa;
Top electrode adds the radio-frequency power 250W that frequency is 27.12MHz, and bottom electrode adds the radio-frequency power 50W that frequency is 13.56MHz, etching 5~10 minutes;
Close radio-frequency power supply, stop air feed, be evacuated to 5x10 -3Pa;
Close extract system, inflated with nitrogen takes out silicon chip after advancing plasma etch chamber to 1 atmospheric pressure.
7. according to the black silicon method of each described preparation of claim 1 to 6, it is characterized in that:
Said silicon chip is monocrystalline silicon piece or polysilicon chip.
CN2011100508871A 2011-03-03 2011-03-03 Method for preparing black silicon Pending CN102655179A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140343A (en) * 2015-08-31 2015-12-09 南京航空航天大学 Polycrystalline black silicon structure and liquid phase preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060147674A1 (en) * 2004-12-30 2006-07-06 Walker Christopher B Jr Durable high index nanocomposites for ar coatings
CN101625973A (en) * 2008-07-10 2010-01-13 国家纳米技术与工程研究院 Method for preparing nano-rod array on silicon chip
CN101692357A (en) * 2009-10-13 2010-04-07 华东师范大学 Method for preparing pile face doped zinc oxide transparent conductive film
CN101700871A (en) * 2009-10-26 2010-05-05 中国科学技术大学 Copper-indium-selenium nanowire array and preparation method and application thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060147674A1 (en) * 2004-12-30 2006-07-06 Walker Christopher B Jr Durable high index nanocomposites for ar coatings
CN101625973A (en) * 2008-07-10 2010-01-13 国家纳米技术与工程研究院 Method for preparing nano-rod array on silicon chip
CN101692357A (en) * 2009-10-13 2010-04-07 华东师范大学 Method for preparing pile face doped zinc oxide transparent conductive film
CN101700871A (en) * 2009-10-26 2010-05-05 中国科学技术大学 Copper-indium-selenium nanowire array and preparation method and application thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140343A (en) * 2015-08-31 2015-12-09 南京航空航天大学 Polycrystalline black silicon structure and liquid phase preparation method thereof

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Application publication date: 20120905