WO1999008317B1 - Integrierte elektrische schaltung mit passivierungsschicht - Google Patents

Integrierte elektrische schaltung mit passivierungsschicht

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Publication number
WO1999008317B1
WO1999008317B1 PCT/DE1998/002236 DE9802236W WO9908317B1 WO 1999008317 B1 WO1999008317 B1 WO 1999008317B1 DE 9802236 W DE9802236 W DE 9802236W WO 9908317 B1 WO9908317 B1 WO 9908317B1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
molecules
passivation layer
metal wires
metal level
Prior art date
Application number
PCT/DE1998/002236
Other languages
English (en)
French (fr)
Other versions
WO1999008317A1 (de
Inventor
Darko Piscevic
Original Assignee
Siemens Ag
Darko Piscevic
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Darko Piscevic filed Critical Siemens Ag
Publication of WO1999008317A1 publication Critical patent/WO1999008317A1/de
Publication of WO1999008317B1 publication Critical patent/WO1999008317B1/de
Priority to US09/498,532 priority Critical patent/US6395454B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
    • Y10T428/268—Monolayer with structurally defined element

Abstract

Die Erfindung betrifft eine integrierte elektrische Schaltung mit einer Metallebene (1), die mit einer Passivierungsschicht versehen ist. Die Passivierungsschicht ist aus einem monomolekularen Film (2), der an der Oberfläche der Metallebene (1) aufgebracht ist, gebildet.

Claims

GEÄNDERTE ANSPRÜCHE[beim Internationalen Büro am 9. März 1999 (09.03.99) eingegangen); ursprüngliche Ansprüche 1-11 geänderte (2 Seiten)]
1. Verfahren zur Herstellung einer integrierten elektrischen Schaltung, bei dem - auf einem Substrat (1) eine oder mehrere dielektrische
Schichten und eine oder mehrere strukturierte Halbleiterschichten sowie mindestens eine Metallebene (11) aufgebracht werden, ein monomolekularer Film (2) aus Molekülen, die wenigstens eine Ankergruppe enthalten, als Passivierungsschicht auf die Metallebene aufgetragen wird und Metalldrähte mit der Metallebene verbunden werden, dadurch gekennzeichnet, daß die Passivierungsschicht aufgetragen wird, bevor die Metalldrähte mit der Metallebene ver- bunden werden, und daß das Verbinden der Metalldrähte mit der Metallebene (11) mit einem Druck, der zum Durchdringen des monomolekularen Films (2) ausreicht, erfolgt.
2. Verfahren zur Herstellung einer integrierten elektrischen Schaltung, bei dem auf einem Substrat (1) eine oder mehrere dielektrische Schichten und eine oder mehrere strukturierte Halbleiterschichten sowie mindestens eine Metallebene (11) aufge- bracht werden,
-- ein monomolekularer Film (2) aus Molekülen, die wenigstens eine Ankergruppe enthalten, als Passivierungsschicht auf die Metallebene aufgetragen wird und Metalldrähte mit der Metallebene verbunden werden, dadurch gekennzeichnet, daß die Passivierungsschicht aufgetragen wird, bevor die Metalldrähte mit der Metallebene verbunden werden, und daß das Verbinden der Metalldrähte mit der Metallebene die folgenden Schritte aufweist: - dem monomolekularen Film wird an für die Verbindung mit den Metalldrähten vorgesehenen Stellen durch elektromagnetische Strahlung gezielt Energie zugeführt, die so groß ist, daß an diesen Stellen die Bindung der Moleküle an das Metall geschwächt wird, - Verbinden der Metalldrähte mit der Metallebene an diesen Stellen.
3. Verfahren nach Anspruch 2, dadurch gekennzeichnet, daß vor dem Verbinden der Metalldrähte mit der Metallebene eine Lösung aufgetragen wird, deren Lösungskraft ausreicht, die Moleküle, deren Bindung an das Metall geschwächt ist, zu lösen.
4. Verfahren nach Anspruch 3, gekennzeichnet durch eine Trocknung mit Stickstoff.
5. Verfahren nach einem der Ansprüche 1 bis 4, dadurch ge- kennzeichnet, daß die Metallebene aus Kupfer, Silber oder
Gold besteht.
6. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, daß die Ankergruppe der Moleküle des onomole- kularen Films ein Thiol ist.
7. Verfahren nach Anspruch 6, dadurch gekennzeichnet, daß das Thiol in hochreinem, vollentsalzten Wasser wird.
8. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, daß die Ankergruppe der Moleküle des monomolekularen Films ein Sufid oder ein Disulfid ist.
9. Verfahren nach einem der Ansprüche 2 bis 8, dadurch ge- kennzeichnet, daß mit einer Quecksilberhöchstdrucklampe bestrahlt wird.
10. Verfahren nach einem der Ansprüche 2 bis 8, dadurch gekennzeichnet, daß mit einem Laser bestrahlt wird.
11. Verfahren nach einem der Ansprüche 2 bis 10, dadurch gekennzeichnet, daß die Strahlung UV-Licht ist.
PCT/DE1998/002236 1997-08-04 1998-08-04 Integrierte elektrische schaltung mit passivierungsschicht WO1999008317A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/498,532 US6395454B1 (en) 1997-08-04 2000-02-04 Integrated electrical circuit with passivation layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19733731.7 1997-08-04
DE19733731A DE19733731A1 (de) 1997-08-04 1997-08-04 Integrierte elektrische Schaltung mit Passivierungsschicht

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/498,532 Continuation US6395454B1 (en) 1997-08-04 2000-02-04 Integrated electrical circuit with passivation layer

Publications (2)

Publication Number Publication Date
WO1999008317A1 WO1999008317A1 (de) 1999-02-18
WO1999008317B1 true WO1999008317B1 (de) 1999-05-27

Family

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Family Applications (1)

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PCT/DE1998/002236 WO1999008317A1 (de) 1997-08-04 1998-08-04 Integrierte elektrische schaltung mit passivierungsschicht

Country Status (3)

Country Link
US (1) US6395454B1 (de)
DE (1) DE19733731A1 (de)
WO (1) WO1999008317A1 (de)

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DE19733731A1 (de) 1999-02-25
WO1999008317A1 (de) 1999-02-18
US6395454B1 (en) 2002-05-28

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